Eigen  3.3.0
 
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NEON/PacketMath.h
1// This file is part of Eigen, a lightweight C++ template library
2// for linear algebra.
3//
4// Copyright (C) 2008-2009 Gael Guennebaud <gael.guennebaud@inria.fr>
5// Copyright (C) 2010 Konstantinos Margaritis <markos@freevec.org>
6// Heavily based on Gael's SSE version.
7//
8// This Source Code Form is subject to the terms of the Mozilla
9// Public License v. 2.0. If a copy of the MPL was not distributed
10// with this file, You can obtain one at http://mozilla.org/MPL/2.0/.
11
12#ifndef EIGEN_PACKET_MATH_NEON_H
13#define EIGEN_PACKET_MATH_NEON_H
14
15namespace Eigen {
16
17namespace internal {
18
19#ifndef EIGEN_CACHEFRIENDLY_PRODUCT_THRESHOLD
20#define EIGEN_CACHEFRIENDLY_PRODUCT_THRESHOLD 8
21#endif
22
23#ifndef EIGEN_HAS_SINGLE_INSTRUCTION_MADD
24#define EIGEN_HAS_SINGLE_INSTRUCTION_MADD
25#endif
26
27#ifndef EIGEN_HAS_SINGLE_INSTRUCTION_CJMADD
28#define EIGEN_HAS_SINGLE_INSTRUCTION_CJMADD
29#endif
30
31// FIXME NEON has 16 quad registers, but since the current register allocator
32// is so bad, it is much better to reduce it to 8
33#ifndef EIGEN_ARCH_DEFAULT_NUMBER_OF_REGISTERS
34#define EIGEN_ARCH_DEFAULT_NUMBER_OF_REGISTERS 16
35#endif
36
37typedef float32x2_t Packet2f;
38typedef float32x4_t Packet4f;
39typedef int32x4_t Packet4i;
40typedef int32x2_t Packet2i;
41typedef uint32x4_t Packet4ui;
42
43#define _EIGEN_DECLARE_CONST_Packet4f(NAME,X) \
44 const Packet4f p4f_##NAME = pset1<Packet4f>(X)
45
46#define _EIGEN_DECLARE_CONST_Packet4f_FROM_INT(NAME,X) \
47 const Packet4f p4f_##NAME = vreinterpretq_f32_u32(pset1<int>(X))
48
49#define _EIGEN_DECLARE_CONST_Packet4i(NAME,X) \
50 const Packet4i p4i_##NAME = pset1<Packet4i>(X)
51
52// arm64 does have the pld instruction. If available, let's trust the __builtin_prefetch built-in function
53// which available on LLVM and GCC (at least)
54#if EIGEN_HAS_BUILTIN(__builtin_prefetch) || EIGEN_COMP_GNUC
55 #define EIGEN_ARM_PREFETCH(ADDR) __builtin_prefetch(ADDR);
56#elif defined __pld
57 #define EIGEN_ARM_PREFETCH(ADDR) __pld(ADDR)
58#elif !EIGEN_ARCH_ARM64
59 #define EIGEN_ARM_PREFETCH(ADDR) __asm__ __volatile__ ( " pld [%[addr]]\n" :: [addr] "r" (ADDR) : "cc" );
60#else
61 // by default no explicit prefetching
62 #define EIGEN_ARM_PREFETCH(ADDR)
63#endif
64
65template<> struct packet_traits<float> : default_packet_traits
66{
67 typedef Packet4f type;
68 typedef Packet4f half; // Packet2f intrinsics not implemented yet
69 enum {
70 Vectorizable = 1,
71 AlignedOnScalar = 1,
72 size = 4,
73 HasHalfPacket=0, // Packet2f intrinsics not implemented yet
74
75 HasDiv = 1,
76 // FIXME check the Has*
77 HasSin = 0,
78 HasCos = 0,
79 HasLog = 0,
80 HasExp = 1,
81 HasSqrt = 0
82 };
83};
84template<> struct packet_traits<int> : default_packet_traits
85{
86 typedef Packet4i type;
87 typedef Packet4i half; // Packet2i intrinsics not implemented yet
88 enum {
89 Vectorizable = 1,
90 AlignedOnScalar = 1,
91 size=4,
92 HasHalfPacket=0 // Packet2i intrinsics not implemented yet
93 // FIXME check the Has*
94 };
95};
96
97#if EIGEN_GNUC_AT_MOST(4,4) && !EIGEN_COMP_LLVM
98// workaround gcc 4.2, 4.3 and 4.4 compilatin issue
99EIGEN_STRONG_INLINE float32x4_t vld1q_f32(const float* x) { return ::vld1q_f32((const float32_t*)x); }
100EIGEN_STRONG_INLINE float32x2_t vld1_f32 (const float* x) { return ::vld1_f32 ((const float32_t*)x); }
101EIGEN_STRONG_INLINE float32x2_t vld1_dup_f32 (const float* x) { return ::vld1_dup_f32 ((const float32_t*)x); }
102EIGEN_STRONG_INLINE void vst1q_f32(float* to, float32x4_t from) { ::vst1q_f32((float32_t*)to,from); }
103EIGEN_STRONG_INLINE void vst1_f32 (float* to, float32x2_t from) { ::vst1_f32 ((float32_t*)to,from); }
104#endif
105
106template<> struct unpacket_traits<Packet4f> { typedef float type; enum {size=4, alignment=Aligned16}; typedef Packet4f half; };
107template<> struct unpacket_traits<Packet4i> { typedef int type; enum {size=4, alignment=Aligned16}; typedef Packet4i half; };
108
109template<> EIGEN_STRONG_INLINE Packet4f pset1<Packet4f>(const float& from) { return vdupq_n_f32(from); }
110template<> EIGEN_STRONG_INLINE Packet4i pset1<Packet4i>(const int& from) { return vdupq_n_s32(from); }
111
112template<> EIGEN_STRONG_INLINE Packet4f plset<Packet4f>(const float& a)
113{
114 const float32_t f[] = {0, 1, 2, 3};
115 Packet4f countdown = vld1q_f32(f);
116 return vaddq_f32(pset1<Packet4f>(a), countdown);
117}
118template<> EIGEN_STRONG_INLINE Packet4i plset<Packet4i>(const int& a)
119{
120 const int32_t i[] = {0, 1, 2, 3};
121 Packet4i countdown = vld1q_s32(i);
122 return vaddq_s32(pset1<Packet4i>(a), countdown);
123}
124
125template<> EIGEN_STRONG_INLINE Packet4f padd<Packet4f>(const Packet4f& a, const Packet4f& b) { return vaddq_f32(a,b); }
126template<> EIGEN_STRONG_INLINE Packet4i padd<Packet4i>(const Packet4i& a, const Packet4i& b) { return vaddq_s32(a,b); }
127
128template<> EIGEN_STRONG_INLINE Packet4f psub<Packet4f>(const Packet4f& a, const Packet4f& b) { return vsubq_f32(a,b); }
129template<> EIGEN_STRONG_INLINE Packet4i psub<Packet4i>(const Packet4i& a, const Packet4i& b) { return vsubq_s32(a,b); }
130
131template<> EIGEN_STRONG_INLINE Packet4f pnegate(const Packet4f& a) { return vnegq_f32(a); }
132template<> EIGEN_STRONG_INLINE Packet4i pnegate(const Packet4i& a) { return vnegq_s32(a); }
133
134template<> EIGEN_STRONG_INLINE Packet4f pconj(const Packet4f& a) { return a; }
135template<> EIGEN_STRONG_INLINE Packet4i pconj(const Packet4i& a) { return a; }
136
137template<> EIGEN_STRONG_INLINE Packet4f pmul<Packet4f>(const Packet4f& a, const Packet4f& b) { return vmulq_f32(a,b); }
138template<> EIGEN_STRONG_INLINE Packet4i pmul<Packet4i>(const Packet4i& a, const Packet4i& b) { return vmulq_s32(a,b); }
139
140template<> EIGEN_STRONG_INLINE Packet4f pdiv<Packet4f>(const Packet4f& a, const Packet4f& b)
141{
142#if EIGEN_ARCH_ARM64
143 return vdivq_f32(a,b);
144#else
145 Packet4f inv, restep, div;
146
147 // NEON does not offer a divide instruction, we have to do a reciprocal approximation
148 // However NEON in contrast to other SIMD engines (AltiVec/SSE), offers
149 // a reciprocal estimate AND a reciprocal step -which saves a few instructions
150 // vrecpeq_f32() returns an estimate to 1/b, which we will finetune with
151 // Newton-Raphson and vrecpsq_f32()
152 inv = vrecpeq_f32(b);
153
154 // This returns a differential, by which we will have to multiply inv to get a better
155 // approximation of 1/b.
156 restep = vrecpsq_f32(b, inv);
157 inv = vmulq_f32(restep, inv);
158
159 // Finally, multiply a by 1/b and get the wanted result of the division.
160 div = vmulq_f32(a, inv);
161
162 return div;
163#endif
164}
165
166template<> EIGEN_STRONG_INLINE Packet4i pdiv<Packet4i>(const Packet4i& /*a*/, const Packet4i& /*b*/)
167{ eigen_assert(false && "packet integer division are not supported by NEON");
168 return pset1<Packet4i>(0);
169}
170
171// Clang/ARM wrongly advertises __ARM_FEATURE_FMA even when it's not available,
172// then implements a slow software scalar fallback calling fmaf()!
173// Filed LLVM bug:
174// https://llvm.org/bugs/show_bug.cgi?id=27216
175#if (defined __ARM_FEATURE_FMA) && !(EIGEN_COMP_CLANG && EIGEN_ARCH_ARM)
176// See bug 936.
177// FMA is available on VFPv4 i.e. when compiling with -mfpu=neon-vfpv4.
178// FMA is a true fused multiply-add i.e. only 1 rounding at the end, no intermediate rounding.
179// MLA is not fused i.e. does 2 roundings.
180// In addition to giving better accuracy, FMA also gives better performance here on a Krait (Nexus 4):
181// MLA: 10 GFlop/s ; FMA: 12 GFlops/s.
182template<> EIGEN_STRONG_INLINE Packet4f pmadd(const Packet4f& a, const Packet4f& b, const Packet4f& c) { return vfmaq_f32(c,a,b); }
183#else
184template<> EIGEN_STRONG_INLINE Packet4f pmadd(const Packet4f& a, const Packet4f& b, const Packet4f& c) {
185#if EIGEN_COMP_CLANG && EIGEN_ARCH_ARM
186 // Clang/ARM will replace VMLA by VMUL+VADD at least for some values of -mcpu,
187 // at least -mcpu=cortex-a8 and -mcpu=cortex-a7. Since the former is the default on
188 // -march=armv7-a, that is a very common case.
189 // See e.g. this thread:
190 // http://lists.llvm.org/pipermail/llvm-dev/2013-December/068806.html
191 // Filed LLVM bug:
192 // https://llvm.org/bugs/show_bug.cgi?id=27219
193 Packet4f r = c;
194 asm volatile(
195 "vmla.f32 %q[r], %q[a], %q[b]"
196 : [r] "+w" (r)
197 : [a] "w" (a),
198 [b] "w" (b)
199 : );
200 return r;
201#else
202 return vmlaq_f32(c,a,b);
203#endif
204}
205#endif
206
207// No FMA instruction for int, so use MLA unconditionally.
208template<> EIGEN_STRONG_INLINE Packet4i pmadd(const Packet4i& a, const Packet4i& b, const Packet4i& c) { return vmlaq_s32(c,a,b); }
209
210template<> EIGEN_STRONG_INLINE Packet4f pmin<Packet4f>(const Packet4f& a, const Packet4f& b) { return vminq_f32(a,b); }
211template<> EIGEN_STRONG_INLINE Packet4i pmin<Packet4i>(const Packet4i& a, const Packet4i& b) { return vminq_s32(a,b); }
212
213template<> EIGEN_STRONG_INLINE Packet4f pmax<Packet4f>(const Packet4f& a, const Packet4f& b) { return vmaxq_f32(a,b); }
214template<> EIGEN_STRONG_INLINE Packet4i pmax<Packet4i>(const Packet4i& a, const Packet4i& b) { return vmaxq_s32(a,b); }
215
216// Logical Operations are not supported for float, so we have to reinterpret casts using NEON intrinsics
217template<> EIGEN_STRONG_INLINE Packet4f pand<Packet4f>(const Packet4f& a, const Packet4f& b)
218{
219 return vreinterpretq_f32_u32(vandq_u32(vreinterpretq_u32_f32(a),vreinterpretq_u32_f32(b)));
220}
221template<> EIGEN_STRONG_INLINE Packet4i pand<Packet4i>(const Packet4i& a, const Packet4i& b) { return vandq_s32(a,b); }
222
223template<> EIGEN_STRONG_INLINE Packet4f por<Packet4f>(const Packet4f& a, const Packet4f& b)
224{
225 return vreinterpretq_f32_u32(vorrq_u32(vreinterpretq_u32_f32(a),vreinterpretq_u32_f32(b)));
226}
227template<> EIGEN_STRONG_INLINE Packet4i por<Packet4i>(const Packet4i& a, const Packet4i& b) { return vorrq_s32(a,b); }
228
229template<> EIGEN_STRONG_INLINE Packet4f pxor<Packet4f>(const Packet4f& a, const Packet4f& b)
230{
231 return vreinterpretq_f32_u32(veorq_u32(vreinterpretq_u32_f32(a),vreinterpretq_u32_f32(b)));
232}
233template<> EIGEN_STRONG_INLINE Packet4i pxor<Packet4i>(const Packet4i& a, const Packet4i& b) { return veorq_s32(a,b); }
234
235template<> EIGEN_STRONG_INLINE Packet4f pandnot<Packet4f>(const Packet4f& a, const Packet4f& b)
236{
237 return vreinterpretq_f32_u32(vbicq_u32(vreinterpretq_u32_f32(a),vreinterpretq_u32_f32(b)));
238}
239template<> EIGEN_STRONG_INLINE Packet4i pandnot<Packet4i>(const Packet4i& a, const Packet4i& b) { return vbicq_s32(a,b); }
240
241template<> EIGEN_STRONG_INLINE Packet4f pload<Packet4f>(const float* from) { EIGEN_DEBUG_ALIGNED_LOAD return vld1q_f32(from); }
242template<> EIGEN_STRONG_INLINE Packet4i pload<Packet4i>(const int* from) { EIGEN_DEBUG_ALIGNED_LOAD return vld1q_s32(from); }
243
244template<> EIGEN_STRONG_INLINE Packet4f ploadu<Packet4f>(const float* from) { EIGEN_DEBUG_UNALIGNED_LOAD return vld1q_f32(from); }
245template<> EIGEN_STRONG_INLINE Packet4i ploadu<Packet4i>(const int* from) { EIGEN_DEBUG_UNALIGNED_LOAD return vld1q_s32(from); }
246
247template<> EIGEN_STRONG_INLINE Packet4f ploaddup<Packet4f>(const float* from)
248{
249 float32x2_t lo, hi;
250 lo = vld1_dup_f32(from);
251 hi = vld1_dup_f32(from+1);
252 return vcombine_f32(lo, hi);
253}
254template<> EIGEN_STRONG_INLINE Packet4i ploaddup<Packet4i>(const int* from)
255{
256 int32x2_t lo, hi;
257 lo = vld1_dup_s32(from);
258 hi = vld1_dup_s32(from+1);
259 return vcombine_s32(lo, hi);
260}
261
262template<> EIGEN_STRONG_INLINE void pstore<float>(float* to, const Packet4f& from) { EIGEN_DEBUG_ALIGNED_STORE vst1q_f32(to, from); }
263template<> EIGEN_STRONG_INLINE void pstore<int>(int* to, const Packet4i& from) { EIGEN_DEBUG_ALIGNED_STORE vst1q_s32(to, from); }
264
265template<> EIGEN_STRONG_INLINE void pstoreu<float>(float* to, const Packet4f& from) { EIGEN_DEBUG_UNALIGNED_STORE vst1q_f32(to, from); }
266template<> EIGEN_STRONG_INLINE void pstoreu<int>(int* to, const Packet4i& from) { EIGEN_DEBUG_UNALIGNED_STORE vst1q_s32(to, from); }
267
268template<> EIGEN_DEVICE_FUNC inline Packet4f pgather<float, Packet4f>(const float* from, Index stride)
269{
270 Packet4f res = pset1<Packet4f>(0.f);
271 res = vsetq_lane_f32(from[0*stride], res, 0);
272 res = vsetq_lane_f32(from[1*stride], res, 1);
273 res = vsetq_lane_f32(from[2*stride], res, 2);
274 res = vsetq_lane_f32(from[3*stride], res, 3);
275 return res;
276}
277template<> EIGEN_DEVICE_FUNC inline Packet4i pgather<int, Packet4i>(const int* from, Index stride)
278{
279 Packet4i res = pset1<Packet4i>(0);
280 res = vsetq_lane_s32(from[0*stride], res, 0);
281 res = vsetq_lane_s32(from[1*stride], res, 1);
282 res = vsetq_lane_s32(from[2*stride], res, 2);
283 res = vsetq_lane_s32(from[3*stride], res, 3);
284 return res;
285}
286
287template<> EIGEN_DEVICE_FUNC inline void pscatter<float, Packet4f>(float* to, const Packet4f& from, Index stride)
288{
289 to[stride*0] = vgetq_lane_f32(from, 0);
290 to[stride*1] = vgetq_lane_f32(from, 1);
291 to[stride*2] = vgetq_lane_f32(from, 2);
292 to[stride*3] = vgetq_lane_f32(from, 3);
293}
294template<> EIGEN_DEVICE_FUNC inline void pscatter<int, Packet4i>(int* to, const Packet4i& from, Index stride)
295{
296 to[stride*0] = vgetq_lane_s32(from, 0);
297 to[stride*1] = vgetq_lane_s32(from, 1);
298 to[stride*2] = vgetq_lane_s32(from, 2);
299 to[stride*3] = vgetq_lane_s32(from, 3);
300}
301
302template<> EIGEN_STRONG_INLINE void prefetch<float>(const float* addr) { EIGEN_ARM_PREFETCH(addr); }
303template<> EIGEN_STRONG_INLINE void prefetch<int>(const int* addr) { EIGEN_ARM_PREFETCH(addr); }
304
305// FIXME only store the 2 first elements ?
306template<> EIGEN_STRONG_INLINE float pfirst<Packet4f>(const Packet4f& a) { float EIGEN_ALIGN16 x[4]; vst1q_f32(x, a); return x[0]; }
307template<> EIGEN_STRONG_INLINE int pfirst<Packet4i>(const Packet4i& a) { int EIGEN_ALIGN16 x[4]; vst1q_s32(x, a); return x[0]; }
308
309template<> EIGEN_STRONG_INLINE Packet4f preverse(const Packet4f& a) {
310 float32x2_t a_lo, a_hi;
311 Packet4f a_r64;
312
313 a_r64 = vrev64q_f32(a);
314 a_lo = vget_low_f32(a_r64);
315 a_hi = vget_high_f32(a_r64);
316 return vcombine_f32(a_hi, a_lo);
317}
318template<> EIGEN_STRONG_INLINE Packet4i preverse(const Packet4i& a) {
319 int32x2_t a_lo, a_hi;
320 Packet4i a_r64;
321
322 a_r64 = vrev64q_s32(a);
323 a_lo = vget_low_s32(a_r64);
324 a_hi = vget_high_s32(a_r64);
325 return vcombine_s32(a_hi, a_lo);
326}
327
328template<> EIGEN_STRONG_INLINE Packet4f pabs(const Packet4f& a) { return vabsq_f32(a); }
329template<> EIGEN_STRONG_INLINE Packet4i pabs(const Packet4i& a) { return vabsq_s32(a); }
330
331template<> EIGEN_STRONG_INLINE float predux<Packet4f>(const Packet4f& a)
332{
333 float32x2_t a_lo, a_hi, sum;
334
335 a_lo = vget_low_f32(a);
336 a_hi = vget_high_f32(a);
337 sum = vpadd_f32(a_lo, a_hi);
338 sum = vpadd_f32(sum, sum);
339 return vget_lane_f32(sum, 0);
340}
341
342template<> EIGEN_STRONG_INLINE Packet4f preduxp<Packet4f>(const Packet4f* vecs)
343{
344 float32x4x2_t vtrn1, vtrn2, res1, res2;
345 Packet4f sum1, sum2, sum;
346
347 // NEON zip performs interleaving of the supplied vectors.
348 // We perform two interleaves in a row to acquire the transposed vector
349 vtrn1 = vzipq_f32(vecs[0], vecs[2]);
350 vtrn2 = vzipq_f32(vecs[1], vecs[3]);
351 res1 = vzipq_f32(vtrn1.val[0], vtrn2.val[0]);
352 res2 = vzipq_f32(vtrn1.val[1], vtrn2.val[1]);
353
354 // Do the addition of the resulting vectors
355 sum1 = vaddq_f32(res1.val[0], res1.val[1]);
356 sum2 = vaddq_f32(res2.val[0], res2.val[1]);
357 sum = vaddq_f32(sum1, sum2);
358
359 return sum;
360}
361
362template<> EIGEN_STRONG_INLINE int predux<Packet4i>(const Packet4i& a)
363{
364 int32x2_t a_lo, a_hi, sum;
365
366 a_lo = vget_low_s32(a);
367 a_hi = vget_high_s32(a);
368 sum = vpadd_s32(a_lo, a_hi);
369 sum = vpadd_s32(sum, sum);
370 return vget_lane_s32(sum, 0);
371}
372
373template<> EIGEN_STRONG_INLINE Packet4i preduxp<Packet4i>(const Packet4i* vecs)
374{
375 int32x4x2_t vtrn1, vtrn2, res1, res2;
376 Packet4i sum1, sum2, sum;
377
378 // NEON zip performs interleaving of the supplied vectors.
379 // We perform two interleaves in a row to acquire the transposed vector
380 vtrn1 = vzipq_s32(vecs[0], vecs[2]);
381 vtrn2 = vzipq_s32(vecs[1], vecs[3]);
382 res1 = vzipq_s32(vtrn1.val[0], vtrn2.val[0]);
383 res2 = vzipq_s32(vtrn1.val[1], vtrn2.val[1]);
384
385 // Do the addition of the resulting vectors
386 sum1 = vaddq_s32(res1.val[0], res1.val[1]);
387 sum2 = vaddq_s32(res2.val[0], res2.val[1]);
388 sum = vaddq_s32(sum1, sum2);
389
390 return sum;
391}
392
393// Other reduction functions:
394// mul
395template<> EIGEN_STRONG_INLINE float predux_mul<Packet4f>(const Packet4f& a)
396{
397 float32x2_t a_lo, a_hi, prod;
398
399 // Get a_lo = |a1|a2| and a_hi = |a3|a4|
400 a_lo = vget_low_f32(a);
401 a_hi = vget_high_f32(a);
402 // Get the product of a_lo * a_hi -> |a1*a3|a2*a4|
403 prod = vmul_f32(a_lo, a_hi);
404 // Multiply prod with its swapped value |a2*a4|a1*a3|
405 prod = vmul_f32(prod, vrev64_f32(prod));
406
407 return vget_lane_f32(prod, 0);
408}
409template<> EIGEN_STRONG_INLINE int predux_mul<Packet4i>(const Packet4i& a)
410{
411 int32x2_t a_lo, a_hi, prod;
412
413 // Get a_lo = |a1|a2| and a_hi = |a3|a4|
414 a_lo = vget_low_s32(a);
415 a_hi = vget_high_s32(a);
416 // Get the product of a_lo * a_hi -> |a1*a3|a2*a4|
417 prod = vmul_s32(a_lo, a_hi);
418 // Multiply prod with its swapped value |a2*a4|a1*a3|
419 prod = vmul_s32(prod, vrev64_s32(prod));
420
421 return vget_lane_s32(prod, 0);
422}
423
424// min
425template<> EIGEN_STRONG_INLINE float predux_min<Packet4f>(const Packet4f& a)
426{
427 float32x2_t a_lo, a_hi, min;
428
429 a_lo = vget_low_f32(a);
430 a_hi = vget_high_f32(a);
431 min = vpmin_f32(a_lo, a_hi);
432 min = vpmin_f32(min, min);
433
434 return vget_lane_f32(min, 0);
435}
436
437template<> EIGEN_STRONG_INLINE int predux_min<Packet4i>(const Packet4i& a)
438{
439 int32x2_t a_lo, a_hi, min;
440
441 a_lo = vget_low_s32(a);
442 a_hi = vget_high_s32(a);
443 min = vpmin_s32(a_lo, a_hi);
444 min = vpmin_s32(min, min);
445
446 return vget_lane_s32(min, 0);
447}
448
449// max
450template<> EIGEN_STRONG_INLINE float predux_max<Packet4f>(const Packet4f& a)
451{
452 float32x2_t a_lo, a_hi, max;
453
454 a_lo = vget_low_f32(a);
455 a_hi = vget_high_f32(a);
456 max = vpmax_f32(a_lo, a_hi);
457 max = vpmax_f32(max, max);
458
459 return vget_lane_f32(max, 0);
460}
461
462template<> EIGEN_STRONG_INLINE int predux_max<Packet4i>(const Packet4i& a)
463{
464 int32x2_t a_lo, a_hi, max;
465
466 a_lo = vget_low_s32(a);
467 a_hi = vget_high_s32(a);
468 max = vpmax_s32(a_lo, a_hi);
469 max = vpmax_s32(max, max);
470
471 return vget_lane_s32(max, 0);
472}
473
474// this PALIGN_NEON business is to work around a bug in LLVM Clang 3.0 causing incorrect compilation errors,
475// see bug 347 and this LLVM bug: http://llvm.org/bugs/show_bug.cgi?id=11074
476#define PALIGN_NEON(Offset,Type,Command) \
477template<>\
478struct palign_impl<Offset,Type>\
479{\
480 EIGEN_STRONG_INLINE static void run(Type& first, const Type& second)\
481 {\
482 if (Offset!=0)\
483 first = Command(first, second, Offset);\
484 }\
485};\
486
487PALIGN_NEON(0,Packet4f,vextq_f32)
488PALIGN_NEON(1,Packet4f,vextq_f32)
489PALIGN_NEON(2,Packet4f,vextq_f32)
490PALIGN_NEON(3,Packet4f,vextq_f32)
491PALIGN_NEON(0,Packet4i,vextq_s32)
492PALIGN_NEON(1,Packet4i,vextq_s32)
493PALIGN_NEON(2,Packet4i,vextq_s32)
494PALIGN_NEON(3,Packet4i,vextq_s32)
495
496#undef PALIGN_NEON
497
498EIGEN_DEVICE_FUNC inline void
499ptranspose(PacketBlock<Packet4f,4>& kernel) {
500 float32x4x2_t tmp1 = vzipq_f32(kernel.packet[0], kernel.packet[1]);
501 float32x4x2_t tmp2 = vzipq_f32(kernel.packet[2], kernel.packet[3]);
502
503 kernel.packet[0] = vcombine_f32(vget_low_f32(tmp1.val[0]), vget_low_f32(tmp2.val[0]));
504 kernel.packet[1] = vcombine_f32(vget_high_f32(tmp1.val[0]), vget_high_f32(tmp2.val[0]));
505 kernel.packet[2] = vcombine_f32(vget_low_f32(tmp1.val[1]), vget_low_f32(tmp2.val[1]));
506 kernel.packet[3] = vcombine_f32(vget_high_f32(tmp1.val[1]), vget_high_f32(tmp2.val[1]));
507}
508
509EIGEN_DEVICE_FUNC inline void
510ptranspose(PacketBlock<Packet4i,4>& kernel) {
511 int32x4x2_t tmp1 = vzipq_s32(kernel.packet[0], kernel.packet[1]);
512 int32x4x2_t tmp2 = vzipq_s32(kernel.packet[2], kernel.packet[3]);
513 kernel.packet[0] = vcombine_s32(vget_low_s32(tmp1.val[0]), vget_low_s32(tmp2.val[0]));
514 kernel.packet[1] = vcombine_s32(vget_high_s32(tmp1.val[0]), vget_high_s32(tmp2.val[0]));
515 kernel.packet[2] = vcombine_s32(vget_low_s32(tmp1.val[1]), vget_low_s32(tmp2.val[1]));
516 kernel.packet[3] = vcombine_s32(vget_high_s32(tmp1.val[1]), vget_high_s32(tmp2.val[1]));
517}
518
519//---------- double ----------
520
521// Clang 3.5 in the iOS toolchain has an ICE triggered by NEON intrisics for double.
522// Confirmed at least with __apple_build_version__ = 6000054.
523#ifdef __apple_build_version__
524// Let's hope that by the time __apple_build_version__ hits the 601* range, the bug will be fixed.
525// https://gist.github.com/yamaya/2924292 suggests that the 3 first digits are only updated with
526// major toolchain updates.
527#define EIGEN_APPLE_DOUBLE_NEON_BUG (__apple_build_version__ < 6010000)
528#else
529#define EIGEN_APPLE_DOUBLE_NEON_BUG 0
530#endif
531
532#if EIGEN_ARCH_ARM64 && !EIGEN_APPLE_DOUBLE_NEON_BUG
533
534// Bug 907: workaround missing declarations of the following two functions in the ADK
535// Defining these functions as templates ensures that if these intrinsics are
536// already defined in arm_neon.h, then our workaround doesn't cause a conflict
537// and has lower priority in overload resolution.
538template <typename T>
539uint64x2_t vreinterpretq_u64_f64(T a)
540{
541 return (uint64x2_t) a;
542}
543
544template <typename T>
545float64x2_t vreinterpretq_f64_u64(T a)
546{
547 return (float64x2_t) a;
548}
549
550typedef float64x2_t Packet2d;
551typedef float64x1_t Packet1d;
552
553template<> struct packet_traits<double> : default_packet_traits
554{
555 typedef Packet2d type;
556 typedef Packet2d half;
557 enum {
558 Vectorizable = 1,
559 AlignedOnScalar = 1,
560 size = 2,
561 HasHalfPacket=0,
562
563 HasDiv = 1,
564 // FIXME check the Has*
565 HasSin = 0,
566 HasCos = 0,
567 HasLog = 0,
568 HasExp = 0,
569 HasSqrt = 0
570 };
571};
572
573template<> struct unpacket_traits<Packet2d> { typedef double type; enum {size=2, alignment=Aligned16}; typedef Packet2d half; };
574
575template<> EIGEN_STRONG_INLINE Packet2d pset1<Packet2d>(const double& from) { return vdupq_n_f64(from); }
576
577template<> EIGEN_STRONG_INLINE Packet2d plset<Packet2d>(const double& a)
578{
579 const double countdown_raw[] = {0.0,1.0};
580 const Packet2d countdown = vld1q_f64(countdown_raw);
581 return vaddq_f64(pset1<Packet2d>(a), countdown);
582}
583template<> EIGEN_STRONG_INLINE Packet2d padd<Packet2d>(const Packet2d& a, const Packet2d& b) { return vaddq_f64(a,b); }
584
585template<> EIGEN_STRONG_INLINE Packet2d psub<Packet2d>(const Packet2d& a, const Packet2d& b) { return vsubq_f64(a,b); }
586
587template<> EIGEN_STRONG_INLINE Packet2d pnegate(const Packet2d& a) { return vnegq_f64(a); }
588
589template<> EIGEN_STRONG_INLINE Packet2d pconj(const Packet2d& a) { return a; }
590
591template<> EIGEN_STRONG_INLINE Packet2d pmul<Packet2d>(const Packet2d& a, const Packet2d& b) { return vmulq_f64(a,b); }
592
593template<> EIGEN_STRONG_INLINE Packet2d pdiv<Packet2d>(const Packet2d& a, const Packet2d& b) { return vdivq_f64(a,b); }
594
595#ifdef __ARM_FEATURE_FMA
596// See bug 936. See above comment about FMA for float.
597template<> EIGEN_STRONG_INLINE Packet2d pmadd(const Packet2d& a, const Packet2d& b, const Packet2d& c) { return vfmaq_f64(c,a,b); }
598#else
599template<> EIGEN_STRONG_INLINE Packet2d pmadd(const Packet2d& a, const Packet2d& b, const Packet2d& c) { return vmlaq_f64(c,a,b); }
600#endif
601
602template<> EIGEN_STRONG_INLINE Packet2d pmin<Packet2d>(const Packet2d& a, const Packet2d& b) { return vminq_f64(a,b); }
603
604template<> EIGEN_STRONG_INLINE Packet2d pmax<Packet2d>(const Packet2d& a, const Packet2d& b) { return vmaxq_f64(a,b); }
605
606// Logical Operations are not supported for float, so we have to reinterpret casts using NEON intrinsics
607template<> EIGEN_STRONG_INLINE Packet2d pand<Packet2d>(const Packet2d& a, const Packet2d& b)
608{
609 return vreinterpretq_f64_u64(vandq_u64(vreinterpretq_u64_f64(a),vreinterpretq_u64_f64(b)));
610}
611
612template<> EIGEN_STRONG_INLINE Packet2d por<Packet2d>(const Packet2d& a, const Packet2d& b)
613{
614 return vreinterpretq_f64_u64(vorrq_u64(vreinterpretq_u64_f64(a),vreinterpretq_u64_f64(b)));
615}
616
617template<> EIGEN_STRONG_INLINE Packet2d pxor<Packet2d>(const Packet2d& a, const Packet2d& b)
618{
619 return vreinterpretq_f64_u64(veorq_u64(vreinterpretq_u64_f64(a),vreinterpretq_u64_f64(b)));
620}
621
622template<> EIGEN_STRONG_INLINE Packet2d pandnot<Packet2d>(const Packet2d& a, const Packet2d& b)
623{
624 return vreinterpretq_f64_u64(vbicq_u64(vreinterpretq_u64_f64(a),vreinterpretq_u64_f64(b)));
625}
626
627template<> EIGEN_STRONG_INLINE Packet2d pload<Packet2d>(const double* from) { EIGEN_DEBUG_ALIGNED_LOAD return vld1q_f64(from); }
628
629template<> EIGEN_STRONG_INLINE Packet2d ploadu<Packet2d>(const double* from) { EIGEN_DEBUG_UNALIGNED_LOAD return vld1q_f64(from); }
630
631template<> EIGEN_STRONG_INLINE Packet2d ploaddup<Packet2d>(const double* from)
632{
633 return vld1q_dup_f64(from);
634}
635template<> EIGEN_STRONG_INLINE void pstore<double>(double* to, const Packet2d& from) { EIGEN_DEBUG_ALIGNED_STORE vst1q_f64(to, from); }
636
637template<> EIGEN_STRONG_INLINE void pstoreu<double>(double* to, const Packet2d& from) { EIGEN_DEBUG_UNALIGNED_STORE vst1q_f64(to, from); }
638
639template<> EIGEN_DEVICE_FUNC inline Packet2d pgather<double, Packet2d>(const double* from, Index stride)
640{
641 Packet2d res = pset1<Packet2d>(0.0);
642 res = vsetq_lane_f64(from[0*stride], res, 0);
643 res = vsetq_lane_f64(from[1*stride], res, 1);
644 return res;
645}
646template<> EIGEN_DEVICE_FUNC inline void pscatter<double, Packet2d>(double* to, const Packet2d& from, Index stride)
647{
648 to[stride*0] = vgetq_lane_f64(from, 0);
649 to[stride*1] = vgetq_lane_f64(from, 1);
650}
651template<> EIGEN_STRONG_INLINE void prefetch<double>(const double* addr) { EIGEN_ARM_PREFETCH(addr); }
652
653// FIXME only store the 2 first elements ?
654template<> EIGEN_STRONG_INLINE double pfirst<Packet2d>(const Packet2d& a) { return vgetq_lane_f64(a, 0); }
655
656template<> EIGEN_STRONG_INLINE Packet2d preverse(const Packet2d& a) { return vcombine_f64(vget_high_f64(a), vget_low_f64(a)); }
657
658template<> EIGEN_STRONG_INLINE Packet2d pabs(const Packet2d& a) { return vabsq_f64(a); }
659
660#if EIGEN_COMP_CLANG && defined(__apple_build_version__)
661// workaround ICE, see bug 907
662template<> EIGEN_STRONG_INLINE double predux<Packet2d>(const Packet2d& a) { return (vget_low_f64(a) + vget_high_f64(a))[0]; }
663#else
664template<> EIGEN_STRONG_INLINE double predux<Packet2d>(const Packet2d& a) { return vget_lane_f64(vget_low_f64(a) + vget_high_f64(a), 0); }
665#endif
666
667template<> EIGEN_STRONG_INLINE Packet2d preduxp<Packet2d>(const Packet2d* vecs)
668{
669 float64x2_t trn1, trn2;
670
671 // NEON zip performs interleaving of the supplied vectors.
672 // We perform two interleaves in a row to acquire the transposed vector
673 trn1 = vzip1q_f64(vecs[0], vecs[1]);
674 trn2 = vzip2q_f64(vecs[0], vecs[1]);
675
676 // Do the addition of the resulting vectors
677 return vaddq_f64(trn1, trn2);
678}
679// Other reduction functions:
680// mul
681#if EIGEN_COMP_CLANG && defined(__apple_build_version__)
682template<> EIGEN_STRONG_INLINE double predux_mul<Packet2d>(const Packet2d& a) { return (vget_low_f64(a) * vget_high_f64(a))[0]; }
683#else
684template<> EIGEN_STRONG_INLINE double predux_mul<Packet2d>(const Packet2d& a) { return vget_lane_f64(vget_low_f64(a) * vget_high_f64(a), 0); }
685#endif
686
687// min
688template<> EIGEN_STRONG_INLINE double predux_min<Packet2d>(const Packet2d& a) { return vgetq_lane_f64(vpminq_f64(a, a), 0); }
689
690// max
691template<> EIGEN_STRONG_INLINE double predux_max<Packet2d>(const Packet2d& a) { return vgetq_lane_f64(vpmaxq_f64(a, a), 0); }
692
693// this PALIGN_NEON business is to work around a bug in LLVM Clang 3.0 causing incorrect compilation errors,
694// see bug 347 and this LLVM bug: http://llvm.org/bugs/show_bug.cgi?id=11074
695#define PALIGN_NEON(Offset,Type,Command) \
696template<>\
697struct palign_impl<Offset,Type>\
698{\
699 EIGEN_STRONG_INLINE static void run(Type& first, const Type& second)\
700 {\
701 if (Offset!=0)\
702 first = Command(first, second, Offset);\
703 }\
704};\
705
706PALIGN_NEON(0,Packet2d,vextq_f64)
707PALIGN_NEON(1,Packet2d,vextq_f64)
708#undef PALIGN_NEON
709
710EIGEN_DEVICE_FUNC inline void
711ptranspose(PacketBlock<Packet2d,2>& kernel) {
712 float64x2_t trn1 = vzip1q_f64(kernel.packet[0], kernel.packet[1]);
713 float64x2_t trn2 = vzip2q_f64(kernel.packet[0], kernel.packet[1]);
714
715 kernel.packet[0] = trn1;
716 kernel.packet[1] = trn2;
717}
718#endif // EIGEN_ARCH_ARM64
719
720} // end namespace internal
721
722} // end namespace Eigen
723
724#endif // EIGEN_PACKET_MATH_NEON_H
@ Aligned16
Definition: Constants.h:230
Namespace containing all symbols from the Eigen library.
Definition: Core:287
EIGEN_DEFAULT_DENSE_INDEX_TYPE Index
The Index type as used for the API.
Definition: Meta.h:33